SH7243 datasheet(44/1726 Pages) RENESAS

tên linh kiện	SH7243

Giải thích chi tiết về linh kiện	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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nhà sản xuất	RENESAS [Renesas Technology Corp]

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44 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 14 of 1692

REJ09B0393-0100

Classification

Symbol

I/O

Name

Function

MD1, MD0

Input

Mode set

Sets the operating mode. Do not

change the signal levels on these pins

during operation.

ASEMD0

Input

Debugging

mode

Enables the E10A-USB emulator

functions.

Input a high level to operate the LSI in

normal mode (not in debugging

mode). To operate it in debugging

mode, apply a low level to this pin on

the user system board.

Operating mode

control

FWE

Input

Flash memory

write enable

Pin for flash memory. Flash memory

can be protected against writing or

erasure through this pin.

RES

Input

Power-on reset

This LSI enters the power-on reset

state when this signal goes low.

MRES

Input

Manual reset

This LSI enters the manual reset state

when this signal goes low.

WDTOVF

Output Watchdog timer

overflow

Outputs an overflow signal from the

WDT.

BREQ

Input

Bus-mastership

request

A low level is input to this pin when an

external device requests the release

of the bus mastership.

System control

BACK

Output Bus-mastership

request

acknowledge

Indicates that the bus mastership has

been released to an external device.

Reception of the

BACK signal informs

the device which has output the

BREQ signal that it has acquired the

bus.

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