SH7243 datasheet(47/1726 Pages) RENESAS

47 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 17 of 1692

REJ09B0393-0100

Classification

Symbol

I/O

Name

Function

TCLKA,

TCLKB,

TCLKC,

TCLKD

Input MTU2 timer clock

input

External clock input pins for the

timer.

TIOC0A,

TIOC0B,

TIOC0C,

TIOC0D

I/O

MTU2 input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input

capture input/output compare

output/PWM output pins.

TIOC1A,

TIOC1B

I/O

MTU2 input

capture/output

compare

(channel 1)

The TGRA_1 and TGRB_1 input

capture input/output compare

output/PWM output pins.

TIOC2A,

TIOC2B

I/O

MTU2 input

capture/output

compare

(channel 2)

The TGRA_2 and TGRB_2 input

capture input/output compare

output/PWM output pins.

TIOC3A,

TIOC3B,

TIOC3C,

TIOC3D

I/O

MTU2 input

capture/output

compare

(channel 3)

The TGRA_3 to TGRD_3 input

capture input/output compare

output/PWM output pins.

TIOC4A,

TIOC4B,

TIOC4C,

TIOC4D

I/O

MTU2 input

capture/output

compare

(channel 4)

The TGRA_4 and TGRB_4 input

capture input/output compare

output/PWM output pins.

Multi-function

timer pulse unit

2 (MTU2)

TIC5U,

TIC5V,

TIC5W

Input MTU2 input

capture

(channel 5)

The TGRU_5, TGRV_5, and

TGRW_5 input capture input/dead

time compensation input pins.

Port output

enable (POE)

POE8 to POE0 Input Port output

control

Request signal input to place the

MTU2 and MTU2S waveform output

pin in the high impedance state

(SH7243 has only

POE8, POE4,

POE3, and POE0).

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