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SH7243 bảng dữ liệu(PDF) 91 Page - Renesas Technology Corp

tên linh kiện SH7243
Giải thích chi tiết về linh kiện  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
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SH7243 bảng dữ liệu(HTML) 91 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 1.00 Jun. 26, 2008 Page 61 of 1692
REJ09B0393-0100
2.5
Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Power-on reset from any state
Manual reset from any state
except software standby mode
Power-on reset state
Manual reset state
Program execution state
Bus-released state
Sleep mode
Software standby mode
Exception
handling state
Exception
handling
source
occurs
Exception
handling
ends
Bus request
generated
Bus request
cleared
STBY bit set
for SLEEP
instruction
Power-down state
Reset canceled
STBY bit cleared
for SLEEP
instruction
Reset state
Bus request
cleared
Bus request
cleared
Bus request
generated
Bus request
generated
Interrupt source or
DMA address error occurs
Figure 2.6 Transitions between Processing States



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