M16CSLASH62 datasheet(157/621 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

142

Figure 1.19.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode selection bit

(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-

output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,

so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P71 (SCL) results in

getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA

transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision

detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop

condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection

interrupt respectively.

The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA

terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt

refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL

terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the

start condition detection, and set to “0” by the stop condition detection.

In the first place, the control bits related to the I2C bus (simplified I2C bus) interface are explained.

Bit 0 of the UART special mode register (037716) is used as the I2C mode selection bit.

Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus)

interface effective.

Table 1.19.9 shows the relation between the I2C mode select bit and respective control workings.

Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.

P70 through P72 conforming to the simplified I C bus

Selector

I/O

Timer

delay

Noize

Filter

Timer

UART2

Selector

(Port P71 output data latch)

I/O

P70/TxD2/SDA

P71/RxD2/SCL

Reception register

CLK

Internal clock

UART2

External clock

Selector

UART2

I/O

Timer

P72/CLK2

Arbitration

Start condition detection

Stop condition detection

Data bus

Falling edge

detection

NACK

ACK

UART2

UART2 transmission/

NACK interrupt

request

UART2 reception/ACK

interrupt request

DMA1 request

9th pulse

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

Port reading

With IICM set to 1, the port terminal is to be readable

even if 1 is assigned to P71 of the direction register.

L-synchronous

output enabling bit

R Q

Bus busy

IICM=1

IICM=0

Bus collision/start, stop

condition detection

interrupt request

Bus collision

detection

Noize

Filter

Transmission

To DMA0, DMA1

Noize

Filter

To DMA0

Figure 1.19.27. Functional block diagram for I2C mode

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