M16CSLASH62 datasheet(89/621 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

Item

Specification

No. of channels

2 (cycle steal method)

Transfer memory space

• From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space

• From a fixed address to a fixed address

(Note that DMA-related registers [002016 to 003F16] cannot be accessed)

Maximum No. of bytes transferred

128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (Note)

________

________ ________

________

Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) or both edge

Timer A0 to timer A4 interrupt requests

Timer B0 to timer B5 interrupt requests

UART0 transfer and reception interrupt requests

UART1 transfer and reception interrupt requests

UART2 transfer and reception interrupt requests

Serial I/O3, 4 interrpt requests

A-D conversion interrupt requests

Software triggers

Channel priority

DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously

Transfer unit

8 bits or 16 bits

Transfer address direction

forward/fixed (forward direction cannot be specified for both source and

destination simultaneously)

Transfer mode

• Single transfer mode

After the transfer counter underflows, the DMA enable bit turns to

“0”, and the DMAC turns inactive

• Repeat transfer mode

After the transfer counter underflows, the value of the transfer counter

reload register is reloaded to the transfer counter.

The DMAC remains active unless a “0” is written to the DMA enable bit.

DMA interrupt request generation timing When an underflow occurs in the transfer counter

Active

When the DMA enable bit is set to “1”, the DMAC is active.

When the DMAC is active, data transfer starts every time a DMA

transfer request signal occurs.

Inactive

• When the DMA enable bit is set to “0”, the DMAC is inactive.

• After the transfer counter underflows in single transfer mode

At the time of starting data transfer immediately after turning the DMAC active, the

value of one of source pointer and destination pointer - the one specified for the

forward direction - is reloaded to the forward direction address pointer, and the value

of the transfer counter reload register is reloaded to the transfer counter.

Writing to register

Registers specified for forward direction transfer are always write enabled.

Registers specified for fixed address transfer are write-enabled when

the DMA enable bit is “0”.

Reading the register

Can be read at any time.

However, when the DMA enable bit is “1”, reading the register set up as the

forward register is the same as reading the value of the forward address pointer.

Table 1.16.1. DMAC specifications

Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable

flag (I flag) nor by the interrupt priority level.

Forward address pointer and

reload timing for transfer

counter

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