M16CSLASH62 datasheet(509/621 Pages) RENESAS

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Interrupt

Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

494

4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits

of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared

with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.

Therefore, setting the interrupt priority level to “0” disables the interrupt.

Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels en-

abled, according to the consist of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = 1

· interrupt request bit = 1

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are

independent, and they are not affected by one another.

Table 4.2.2. Interrupt levels enabled according

to the contents of the IPL

Table 4.2.1. Settings of interrupt priority levels

When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in

the following timing:

• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction

that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.

• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes

effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the

instruction used.

• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes

effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in

the instruction used.

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL2 IPL1 IPL0

IPL

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