M16CSLASH62 datasheet(508/621 Pages) RENESAS

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Interrupt

Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

493

instruction

REIT

Interrupt sequence

Time

Interrupt request generated

Determination whether or not to

accept interrupt request

instruction

FSET I

Interrupt sequence

Next instruction

Interrupt request generated

Determination whether or not to

accept interrupt request

When changed by REIT instruction

When changed by FCLR, FSET, POPC, or LDC instruction

(If I flag is changed from 0 to 1 by REIT instruction)

(If I flag is changed from 0 to 1 by FSET instruction)

Time

Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt

4.2.1 Interrupt Enable Flag

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this

flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set

to “0” after reset.

The content is changed when the I flag is changed causes the acceptance of the interrupt request in the

following timing:

• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes

effect as the REIT instruction is executed.

• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the

acceptance of the interrupt is effective as the next instruction is executed.

4.2.2 Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is

accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The

interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").

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