M16CSLASH62A datasheet(83/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Precautions for Interrupts

1-64

Precautions for Interrupts

(1) Reading address 0000016

• When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and

interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.

Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt

source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.

Do not read address 0000016 by software.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt

before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in

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the stack pointer before accepting an interrupt.

When using the NMI interrupt, initialize the stack

pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-

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ing any interrupts including the NMI interrupt is prohibited.

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(3) The NMI interrupt

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•The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if

unused. Be sure to work on it.

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• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register

allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time

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when the NMI interrupt is input.

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• Do not reset the CPU with the input to the NMI pin being in the “L” state.

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• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to

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the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned

down.

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• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to

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the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.

In this instance, the CPU is returned to the normal state by a later interrupt.

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• Signals input to the NMI pin require an “L” level of 1 clock or more, from the operation clock of the CPU.

(4) External interrupt

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• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0

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through INT5 regardless of the CPU operation clock.

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• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”.

After changing the polarity, set the interrupt request bit to “0”. Figure 1.11.13 shows the procedure for

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changing the INT interrupt generate factor.

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