M16CSLASH62A datasheet(49/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control

1-30

Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without

Wait)

Example 1) After access the external area, both the address signal and

the chip select signal change concurrently in the next cycle.

In this example, after access to the external area(i), an access to the area

indicated by the other chip select signal(j) will occur in the next cycle. In

this case, both the address bus and the chip select signal change between

the two cycles.

Note : These examples show the address bus and chip select signal within the successive two cycles.

According to the combination of these examples, the chip select can be elongated to over 2cycles.

BCLK

Read/Write

signal

Data bus

Address bus

Chip select

(CS i)

Access to the

External Area( i )

Chip select

(CS j)

Access to the Other

External Area( j )

Address

Data

Example 2) After access the external area, only the chip select signal

changes in the next cycle (the address bus does not change).

In this example, an access to the internal ROM or the internal RAM in the

next cycle will occur, after access to the external area. In this case, the

chip select signal changes between the two cycles, but the address does

not change.

Example 4) After access the external area, either the address signal and

the chip select signal do not change in the next cycle.

In this example, any access to any area does not occur in the next cycle

(either instruction prefetch does not occur). In this case,either the address

bus and chip select signal do not change between the two cycles.

Example 3) After access the external area, only the address bus changes

in the next cycle (the chip select signal does not change).

In this example, after access to the external area(i), an access to the area

indicated by the same chip select signal(i) will occur in the next cycle. In

this case, the address bus changes between the two cycles, but the chip

select signal does not change.

BCLK

Access to the

External Area

Internal ROM/RAM

Access

Read/Write

signal

Data bus

Address bus

Chip select

Address

Data

BCLK

Access to the

External Area

No Access

Read/Write

signal

Data bus

Address bus

Chip select

Address

Data

BCLK

Access to the

External Area( i )

Access to the Same

External Area( i )

Read/Write

signal

Data bus

Address bus

Chip select

(CS i)

Address

Data

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