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M16C/62A bảng dữ liệu(PDF) 71 Page - Renesas Technology Corp |
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M16C/62A bảng dữ liệu(HTML) 71 Page - Renesas Technology Corp |
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71 / 615 page ![]() Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 1-52 Figure 1.11.3. Interrupt control registers Symbol Address When reset INTiIC(i=3) 004416 XX00X0002 SiIC/INTjIC (i=4, 3) 004816, 004916 XX00X0002 (j=5, 4) 004816, 004916 XX00X0002 INTiIC(i=0 to 2) 005D16 to 005F16 XX00X0002 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 ILVL0 IR POL Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” ILVL1 ILVL2 Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. (Note 1) Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Bit name Function Bit symbol W R Symbol Address When reset TBiIC(i=3 to 5) 004516 to 004716 XXXXX0002 BCNIC 004A16 XXXXX0002 DMiIC(i=0, 1) 004B16, 004C16 XXXXX0002 KUPIC 004D16 XXXXX0002 ADIC 004E16 XXXXX0002 SiTIC(i=0 to 2) 005116, 005316, 004F16 XXXXX0002 SiRIC(i=0 to 2) 005216, 005416, 005016 XXXXX0002 TAiIC(i=0 to 4) 005516 to 005916 XXXXX0002 TBiIC(i=0 to 2) 005A16 to 005C16 XXXXX0002 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. (Note 1) Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 |
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