M16CSLASH62 datasheet(137/615 Pages) RENESAS

137 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock synchronous serial I/O mode

1-118

(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2

and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the

UARTi transmit/receive mode register.

Table 1.16.2. Specifications of clock synchronous serial I/O mode (1)

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Transfer clock

• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816

= “0”) : fi/ 2(n+1) (Note 1)

fi = f1, f8, f32

• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816

= “1”) : Input from CLKi pin

Transmission/reception control

_______

• CTS function, RTS function, CTS and RTS function invalid: selectable

Transmission start condition

• To start transmission, the following requirements must be met:

_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

_______

_ When CTS function selected, CTS input level = “L”

• Furthermore, if external clock is selected, the following requirements must also be met:

_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:

CLKi input level = “H”

_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:

CLKi input level = “L”

Reception start condition

• To start reception, the following requirements must be met:

_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”

_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

• Furthermore, if external clock is selected, the following requirements must

also be met:

_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:

CLKi input level = “H”

_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:

CLKi input level = “L”

• When transmitting

_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at

address 037D16) = “0”: Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

• When receiving

_ Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 2)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

Interrupt request

generation timing

Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.

Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

M16C/62 bảng dữ liệu(PDF) 137 Page - Renesas Technology Corp

M16C/62 bảng dữ liệu(HTML) 137 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL