M16CSLASH26 datasheet(148/239 Pages) RENESAS

148 / 239 page

Renesas Technology Corp.

UART2 Special Mode Register

142

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

TxD2/SDA2

RxD2/SCL2

CLK

control

CLK2

Falling edge

detection

UART2 reception/ACK interrupt

request, DMA1 request

To DMA0, DMA1

I/O

Timer

UARTi

Timer

UART2

IICM=1

IICM=0

or IICM2=1

IICM=1

and IICM2=0

SDHI

Noize

Filter

Timer

UARTi

UART2

I/O

NACK

ACK

UART2

UARTi

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

I/O

ALS

IICM=0

SWC2

Falling edge of 9 bit

SWC

IICM=1

and IICM2=0

IICM=0

or IICM2=1

Selector

Noize

Filter

Noize

Filter

With IICM set to 1, the port terminal is to be readable

even if 1 is assigned to P71 of the direction register.

Port reading

External clock

Internal clock

9th pulse

Bus collision

detection

Bus collision/start, stop condition

detection interrupt request

UART2 transmission/NACK

interrupt request

Start condition

detection

Stop condition

detection

L-synchronous

output enabling

bit

(Port P71 output data latch)

Data bus

Reception register

Bus busy

Transmission

Arbitration

Analog

delay

Figure 1.15.28. Functional block diagram for I2C mode

Figure 1.15.28 shows the functional block diagram for I2C mode.

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