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M16C/26 bảng dữ liệu(PDF) 36 Page - Renesas Technology Corp |
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M16C/26 bảng dữ liệu(HTML) 36 Page - Renesas Technology Corp |
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36 / 239 page ![]() Renesas Technology Corp. Clock Generating Circuit 30 M16C/26 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Clock Control Figure 1.8.3 shows the block diagram of the clock generating circuit. Figure 1.8.3. Clock generating circuit CM21 fC32 CM02, CM04, CM05, CM06, CM07: CM0 register bits CM10, CM11, CM16, CM17: CM1 register bits PCLK0, PCLK1: PCLK register bits CM21, CM27 : CM2 register bits 1/32 Main clock generating circuit fC CM02 CM04 CM10=1(stop mode) Q S R WAIT instruction CM05 Q S R NMI Interrupt request level judgment output RESET Software reset fC CM07=0 CM07=1 Divider a d 1/2 1/2 1/2 1/2 CM06=0 CM17–CM16=002 CM06=0 CM17–CM16=012 CM06=0 CM17–CM16=102 CM06=1 CM06=0 CM17–CM16=112 d a Details of divider Sub-clock generating circuit XCIN XCOUT XOUT XIN f8 f32 c b b 1/2 c f32SIO f8SIO fAD f1 e e 1/2 1/4 1/8 1/16 1/32 PCLK0=1 CM21 CM20 Ring oscillator Sub-clock Ring oscillator clock BCLK PCLK0=0 f2 f1SIO PCLK1=1 PCLK1=0 f2SIO Main clock Oscillation stop, re- oscillation detection circuit 0 1 0 1 |
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