M16CSLASH26 datasheet(75/239 Pages) RENESAS

75 / 239 page

DMAC

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

DMAi control register

Symbol

Address

When reset

DMiCON(i=0,1)

002C16, 003C16

00000X002

Bit name

F unction

Bit symbol

Transfer unit bit select bit

0 : 16 bits

1 : 8 bits

DMBIT

DMASL

DMAS

DMAE

Repeat transfer mode

select bit

0 : Single transfer

1 : Repeat transfer

DMA request bit (Note 1)

0 : DMA not requested

1 : DMA requested

0 : Disabled

1 : Enabled

0 : Fixed

1 : Forward

DMA enable bit

Source address direction

select bit (Note 3)

Destination address

direction select bit (Note 3)

0 : Fixed

1 : Forward

DSD

DAD

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Note 1: DMA request can be cleared by resetting the bit.

Note 2: This bit can only be set to 0 .

Note 3: Source address direction select bit and destination address direction select bit

cannot be set to 1 simultaneously.

(Note 2)

DMA1 request cause select register

Symbol

Address

When reset

DM1SL

03BA16

0016

Function

Bit symbol

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Software DMA

request bit

If software trigger is selected, a

DMA request is generated by

setting this bit to 1 (When read,

the value of this bit is always 0 )

DSR

b3 b2 b1 b0

0 0 0 1 : Software trigger

0 0 1 0 : Timer A0

0 0 1 1 : Timer A1

0 1 0 0 : Timer A2

0 1 0 1 : Timer A3 (DMS=0)

0 1 1 0 : Timer A4 (DMS=0)

0 1 1 1 : Timer B0 (DMS=0)

1 0 0 0 : Timer B1

1 0 0 1 : Timer B2

1 0 1 0 : UART0 transmit

1 0 1 1 : UART0 receive

1 1 0 0 : UART2 transmit

1 1 0 1 : UART2 receive/ACK2

1 1 1 0 : A-D conversion

1 1 1 1 : UART1 receive

0 0 0 0 : Falling edge of INT1 pin

Bit name

DMA request cause

expansion select bit

DMS

0 : Normal

1 : Expanded cause

/two edges of INT1 (DMS=1)

Figure 1.11.3. DMAC register (2)

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