M16CSLASH26 datasheet(145/239 Pages) RENESAS

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Clock Asynchronous Serial I/O (UART) Mode

139

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

(a) Function to output a parity error signal

During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you

can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission,

comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is as-

signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.

Therefore parity error signals can be detected by a transmission completion interrupt program. Figure

1.15.25 shows the output timing of the parity error signal.

Figure 1.15.25. Output timing of the parity error signal

ST : Start bit

P : Even Parity

SP : Stop bit

Hi-Z

Transfer

clock

RxD2

TxD2

Receive

complete flag

LSB first

(b) Direct format/inverse format

Connecting the SIM card allows you to switch between direct format and inverse format. If you choose

the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted

and output from TxD2.

Figure 1.15.26 shows the SIM interface format.

Figure 1.15.26. SIM interface format

P : Even parity

Transfer

clcck

TxD2

(direct)

TxD2

(inverse)

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