R8CSLASH15 datasheet(168/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 156 of 253

REJ09B0164-0210

Figure 15.13

Sample Flowchart for Data Transmit (Clock Synchronous Communication Mode)

Start

Initialization

Read TDRE bit in SSSR register

SSSR register

TEND bit

← 0(1)

End

TDRE=1 ?

Write transmit data to SSTDR register

Data transmit

continued?

Read TEND bit in SSSR register

TEND=1 ?

Yes

Yes (2)

Yes

SSER register

TE bit

← 0

(1)

(2)

(3)

(1) After reading the SSSR register and confirming

that the TDRE bit is set to “1”, write the transmit

data to the SSTDR register. When write the

transmit data to the SSTDR register, the TDRE bit

is automatically set to “0”.

(2) Determine whether data transmit is continued

(3) When the data transmit is completed, the TEND

bit is set to “1”. Set the TEND bit to “0” and the TE

bit to “0” and complete transmit mode.

NOTES:

1. Write “0” after reading “1” to set the TEND bit to “0”.

2. When setting the microcomputer to the slave device, ensure the TEND bit is set to “1” (data transmit ends)

and write the following transmit data to the SSTDR register. When setting the microcomputer to the master

device, continuous transmit is enabled.

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