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SH7052 bảng dữ liệu(PDF) 288 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 bảng dữ liệu(HTML) 288 Page - Renesas Technology Corp

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262
• Bit 2—Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by
the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 2: ICE0C
Description
0
ICI0C interrupt requested by ICF0C is disabled
(Initial value)
1
ICI0C interrupt requested by ICF0C is enabled
• Bit 1—Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by
the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 1: ICE0B
Description
0
ICI0B interrupt requested by ICF0B is disabled
(Initial value)
1
ICI0B interrupt requested by ICF0B is enabled
• Bit 0—Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by
the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 0: ICE0A
Description
0
ICI0A interrupt requested by ICF0A is disabled
(Initial value)
1
ICI0A interrupt requested by ICF0A is enabled
Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B)
TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and
overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
8
——
——
———
OVE1A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
IME1H
IME1G
IME1F
IME1E
IME1D
IME1C
IME1B
IME1A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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