SH7052 datasheet(254/919 Pages) RENESAS

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• Bits 6 to 4—I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2

to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to

IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function.

Bit 6:

IOxx2

Bit 5:

IOxx1

Bit 4:

IOxx0

Description

GR is an output

compare register

Compare-match disabled; pin output

undefined

(Initial value)

0 output on GR compare-match

1 output on GR compare-match

Toggle output on GR compare-match

GR is an input

capture register

Input capture disabled (input capture by

channel 3 and 9 compare-match

enabled) (In channel 3 only, GR cannot

be written to)

Input capture in GR on rising edge at

TIOxx pin (GR cannot be written to)

Input capture in GR on falling edge at

TIOxx pin (GR cannot be written to)

Input capture in GR on both rising and

falling edges at TIOxx pin (GR cannot be

written to)

xx = 3B, 4B, 5B, 3D, 4D, or 5D

• Bit 3—Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C,

CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT)

clearing.

Bit 3: CCIxx

Description

TCNT clearing disabled

(Initial value)

TCNT cleared on GR compare-match

xx = 3A, 4A, 5A, 3C, 4C, or 5C

TCNT is cleared on compare-match only when GR is functioning as an output compare

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