SH7052 datasheet(210/919 Pages) RENESAS

210 / 919 page

184

Table 10.3

ATU-II Registers (cont)

Channel

Name

Abbrevia-

tion

R/W

Initial

Value

Address

Access Size (Bits)

Timer status register

TSR1A

R/(W)* H'0000 H'FFFFF45E 16

Timer status register

TSR1B

R/(W)* H'0000 H'FFFFF460

Timer interrupt enable

TIER1A

R/W

H'0000 H'FFFFF462

Timer interrupt enable

TIER1B

R/W

H'0000 H'FFFFF464

Trigger mode register

TRGMDR

R/W

H'00

H'FFFFF466

Free-running counter

TCNT2A

R/W

H'0000 H'FFFFF600

Free-running counter

TCNT2B

R/W

H'0000 H'FFFFF602

General register 2A

GR2A

R/W

H'FFFF H'FFFFF604

General register 2B

GR2B

R/W

H'FFFF H'FFFFF606

General register 2C

GR2C

R/W

H'FFFF H'FFFFF608

General register 2D

GR2D

R/W

H'FFFF H'FFFFF60A

General register 2E

GR2E

R/W

H'FFFF H'FFFFF60C

General register 2F

GR2F

R/W

H'FFFF H'FFFFF60E

General register 2G

GR2G

R/W

H'FFFF H'FFFFF610

General register 2H

GR2H

R/W

H'FFFF H'FFFFF612

Output compare

OCR2A

R/W

H'FFFF H'FFFFF614

Output compare

OCR2B

R/W

H'FFFF H'FFFFF616

Output compare

OCR2C

R/W

H'FFFF H'FFFFF618

Output compare

OCR2D

R/W

H'FFFF H'FFFFF61A

Output compare

OCR2E

R/W

H'FFFF H'FFFFF61C

Output compare

OCR2F

R/W

H'FFFF H'FFFFF61E

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