SH7052 datasheet(197/919 Pages) RENESAS

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Table 9.8

Transfer Conditions and Register Set Values for Transfer between External

Memory and SCI1 Transmitting Side

Transfer Conditions

Value

Transfer source: external memory

SAR3

H'00400000

Value stored in address H'00400000

—

H'00450000

Value stored in address H'00450000

—

H'55

Transfer destination: on-chip SCI TDR1

DAR3

H'FFFFF00B

Transfer count: 10 times

DMATCR3

H'0000000A

Transfer source address: incremented

CHCR3

H'10031001

Transfer destination address: fixed

Transfer request source: SCI1 (TDR1)

Bus mode: cycle-steal

Transfer unit: byte

Interrupt request not generated at end of transfer

DMAC master enable on

DMAOR

H'0001

When indirect address mode is on, the data stored in the address set in SAR is not used as the

transfer source data. In the case of indirect addressing, the value stored in the SAR address is read,

then that value is used as the address and the data read from that address is used as the transfer

source data, then that data is stored in the address designated by DAR.

In the table 9.8 example, when a transfer request from TDR1 of SCI1 is generated, a read of the

address located at H'00400000, which is the value set in SAR3, is performed first. The data

H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000

value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is

stored in the H'00450000 address. It then writes the value H'55 to address H'FFFFF00B designated

by DAR3 to complete one indirect address transfer.

With indirect addressing, the first executed data read from the address set in SAR3 always results

in a longword size transfer regardless of the TS0 and TS1 bit designations for transfer data size.

However, the transfer source address fixed and increment or decrement designations are according

to the SM0 and SM1 bits. Consequently, despite the fact that the transfer data size designation is

byte in this example, the SAR3 value at the end of one transfer is H'00400004. The write operation

is exactly the same as an ordinary dual address transfer write operation.

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