SH7052 datasheet(184/919 Pages) RENESAS

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Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,

and written to the transfer destination during the write cycle, so transfer is conducted in two bus

cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external

memory transfer shown in figure 9.3, data is read from one of the memories by the DMAC during

a read cycle, then written to the other external memory during the subsequent write cycle. Figure

9.4 shows the timing for this operation.

Data buffer

Memory

Transfer source

module

Transfer destination

module

Memory

Transfer source

module

Transfer destination

module

SAR

DAR

Data buffer

SAR

DAR

The SAR value is taken as the address, and data is read from the transfer source

module and stored temporarily in the DMAC.

1st bus cycle

2nd bus cycle

The DAR value is taken as the address, and data stored in the DMAC's data

buffer is written to the transfer destination module.

DMAC

Figure 9.3 Direct Address Operation in Dual Address Mode

SH7052 bảng dữ liệu(PDF) 184 Page - Renesas Technology Corp