SH7052 datasheet(169/919 Pages) RENESAS

tên linh kiện	SH7052

Giải thích chi tiết về linh kiện	SuperHTM RISC engine

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143

Bit:

Initial value:

—

R/W:

R/W

Bit:

…

……

Initial value:

—

…

—

R/W:

R/W

…

R/W

9.2.2

DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)

DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit readable/writable registers

that specify the destination address of a DMA transfer. These registers have a count function, and

during a DMA transfer, they indicate the next destination address.

Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when

performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.

The value after a power-on reset and in standby mode is undefined.

Bit:

Initial value:

—

R/W:

R/W

Bit:

…

……

Initial value:

—

…

—

R/W:

R/W

…

R/W

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