SH7052 datasheet(136/919 Pages) RENESAS

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7.4

Examples of Use

7.4.1

Break on CPU Instruction Fetch Cycle

1. Register settings:

UBARH = H'0000

UBARL = H'0404

UBBR = H'0054

UBCR = H'0000

Conditions set:

Address: H'00000404

Bus cycle: CPU, instruction fetch, read

(operand size not included in conditions)

Interrupt requests enabled

A user break interrupt will occur before the instruction at address H'00000404. If it is possible

for the instruction at H'00000402 to accept an interrupt, the user break exception processing

will be executed after execution of that instruction. The instruction at H'00000404 is not

executed. The PC value saved is H'00000404.

2. Register settings:

UBARH = H'0015

UBARL = H'389C

UBBR = H'0058

UBCR = H'0000

Conditions set:

Address: H'0015389C

Bus cycle: CPU, instruction fetch, write

(operand size not included in conditions)

Interrupt requests enabled

A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.

3. Register settings:

UBARH = H'0003

UBARL = H'0147

UBBR = H'0054

UBCR = H'0000

Conditions set:

Address: H'00030147

Bus cycle: CPU, instruction fetch, read

(operand size not included in conditions)

Interrupt requests enabled

A user break interrupt does not occur because the instruction fetch was performed for an even

address. However, if the first instruction fetch address after the branch is an odd address set by

these conditions, user break interrupt exception processing will be carried out after address

error exception processing.

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