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SH7052 bảng dữ liệu(PDF) 697 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7052 bảng dữ liệu(HTML) 697 Page - Renesas Technology Corp

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19.6.2
Port E Data Register (PEDR)
Bit:
15
14
13
12
11
10
9
8
PE15
DR
PE14
DR
PE13
DR
PE12
DR
PE11
DR
PE10
DR
PE9
DR
PE8
DR
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
PE7
DR
PE6
DR
PE5
DR
PE4
DR
PE3
DR
PE2
DR
PE1
DR
PE0
DR
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits
PE15DR to PE0DR correspond to pins PE15/A15 to PE0/A0.
When a pin functions as a general output, if a value is written to PEDR, that value is output
directly from the pin, and if PEDR is read, the register value is returned directly regardless of the
pin state. When the
POD pin is driven low, general outputs go to the high-impedance state
regardless of the PEDR value. When the
POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PEDR is read the pin state, not the register value, is
returned directly. If a value is written to PEDR, although that value is written into PEDR it does
not affect the pin state. Table 19.10 summarizes port E data register read/write operations.
PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.



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