SH7052 datasheet(605/919 Pages) RENESAS

605 / 919 page

579

16.4.2

Scan Mode

Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode

is selected for A/D0 by setting the ADM1 and ADM0 bits in A/D control/status register 0 or 1

(ADSCR0) to 01 (4-channel scan mode), or 11 (12-channel scan mode).

For A/D1, scan mode is selected by setting the ADM1 and ADM0 bits in A/D control/status

ADST bit is set to 1 in the A/D control register (ADCR), single-cycle scanning is performed.

When the ADCS bit is set to 1 and the ADST bit is set to 1, continuous scanning is performed.

In scan mode, A/D conversion is performed in low-to-high analog input channel number order

(AN0, AN1 ... AN11, AN12, AN13 ... AN15).

In single-cycle scanning, the ADF bit in ADCSR is set to 1 when conversion has been performed

once on all the set channels, and the ADST bit is automatically cleared to 0.

In continuous scanning, the ADF bit in ADCSR is set to 1 when conversion ends on all the set

channels. To stop A/D conversion, write 0 to the ADST bit.

If the ADIE bit in ADCSR is set to 1 when ADF is set to 1, an ADI interrupt (ADI0, ADI1, or

ADI2) is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If

the DMAC is activated by the ADI interrupt, ADF is cleared to 0 automatically.

An example of the operation when analog inputs 0 to 11 (AN0 to AN11) are selected and A/D

conversion is performed in single-cycle scan mode is described below. Figure 16.4 shows the

operation timing for this example.

1. 12-channel scan mode is selected (ADM1 = 1, ADM0 = 1), single-cycle scan mode is selected

(ADCS = 0), analog input channels AN0 to AN11 are selected (CH3 = 0, CH2 = 0, CH1 = 1,

CH0 = 1), and A/D conversion is started.

2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0.

Next, conversion of the second channel (AN1) starts automatically.

3. Conversion proceeds in the same way through the 12th channel (AN11).

4. When conversion is completed for all the selected channels (AN0 to AN11), the ADF flag is

set to 1, the ADST bit is cleared to 0 automatically, and A/D conversion stops. If the ADIE bit

is 1, an ADI interrupt is requested after A/D conversion ends.

SH7052 bảng dữ liệu(PDF) 605 Page - Renesas Technology Corp