SH7052 datasheet(498/919 Pages) RENESAS

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472

0/1

TDRE

TEND

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idling

(marking)

TXI

interrupt

request

TXI interrupt

handler writes

data in TDR

and clears

TDRE to 0

TXI interrupt

request

TEI interrupt request

1 frame

0/1

Figure 14.6 SCI Transmit Operation in Asynchronous Mode

(Example: 8-Bit Data with Parity and One Stop Bit)

Receiving Serial Data (Asynchronous Mode): Figures 14.7 and 14.8 show a sample flowchart

for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the

flowchart).

1. SCI initialization: Set the RxD pin using the PFC.

2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,

and FER bits of SSR to identify the error. After executing the necessary error handling, clear

ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to

1. When a framing error occurs, the RxD pin can be read to detect the break state.

3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF

is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.

The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.

4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the

stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt

(RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.

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