SH7052 datasheet(457/919 Pages) RENESAS

457 / 919 page

431

13.2.2

Compare Match Timer Control/Status Register (CMCSR)

The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the

occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the

clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby

modes.

Bit:

——

———

—

Initial value:

R/W:

Bit:

CMF

CMIE

—

CKS1

CKS0

Initial value:

R/W:

R/(W)*

R/W

Note: * The only value that can be written is a 0 to clear the flag.

• Bits 15 to 8 and 5 to 2—Reserved: These bits always read 0. The write value should always be

• Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and

CMCOR values have matched.

Bit 7: CMF

Description

CMCNT and CMCOR values have not matched

(Initial value)

[Clearing condition]

Write 0 to CMF after reading 1 from it

CMCNT and CMCOR values have matched

• Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a

compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF =

1).

Bit 6: CMIE

Description

Compare match interrupt (CMI) disabled

(Initial value)

Compare match interrupt (CMI) enabled

SH7052 bảng dữ liệu(PDF) 457 Page - Renesas Technology Corp

SH7052 bảng dữ liệu(HTML) 457 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL