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SH7052 bảng dữ liệu(PDF) 356 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 bảng dữ liệu(HTML) 356 Page - Renesas Technology Corp

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330
• Bit 2—Noise Canceler Enable (NCE): Enables or disables the noise canceler function.
Bit 2: NCE
Description
0
Noise canceler function is disabled
(Initial value)
1
Noise canceler function is enabled
• Bits 1 and 0—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10
external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s).
Bit 1: CKEG1
Bit 0: CKEG0
Description
0
0
TI10 input disabled
(Initial value)
1
TI10 input rising edges detected
1
0
TI10 input falling edges detected
1
TI10 input rising and falling edges both detected
Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates
the occurrence of channel 10 input capture or compare-match.
Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is
enabled by the corresponding bit in timer interrupt enable register 10 (TIER10).
TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
——
——
CMF10G CMF10B ICF10A CMF10A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only 0 can be written, to clear the flag.
• Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0.



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