H838532H datasheet(312/508 Pages) RENESAS

312 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 292 of 484

REJ09B0436-0100

Bit 5: Parity enable (PE)

Bit 5 selects whether a parity bit is to be added during transmission and checked during reception

in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,

irrespective of the bit 5 setting.

Bit 5

Description

Parity bit addition and checking disabled*

(initial value)

Parity bit addition and checking enabled*

Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit

data before it is sent, and the received parity bit is checked against the parity

designated by bit PM.

2. For the case where 5-bit data is selected, see table 10.11.

Bit 4: Parity mode (PM)

Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit

setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and

checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity

bit addition and checking is disabled.

Bit 4

Description

Even parity*

(initial value)

Odd parity*

Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total

number of 1 bits in the transmit data plus the parity bit is an even number; in reception,

a check is carried out to confirm that the number of 1 bits in the receive data plus the

parity bit is an even number.

2. When odd parity is selected, a parity bit is added in transmission so that the total

number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a

check is carried out to confirm that the number of 1 bits in the receive data plus the

parity bit is an odd number.

H838532H bảng dữ liệu(PDF) 312 Page - Renesas Technology Corp