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310 / 508 page  Section 10 Serial Communication Interface Rev. 1.00 May 30, 2008 Page 290 of 484 REJ09B0436-0100 10.2.3 Transmit Shift Register (TSR) Bit Read/Write 7 — 6 — 5 — 4 — 3 — 0 — 2 — 1 — TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD 3x pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register (SSR)). TSR cannot be read or written directly by the CPU. 10.2.4 Transmit Data Register (TDR) Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 0 TDR0 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode. |
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