H838532H datasheet(62/508 Pages) RENESAS

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Section 2 CPU

Rev. 1.00 May 30, 2008 Page 42 of 484

REJ09B0436-0100

(2) Register Indirect

@ERn

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of

which contain the address of the operand on memory.

(3) Register Indirect with Displacement

@(d:16, ERn) or @(d:24, ERn)

A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the lower 24 bits of the sum the address of a

memory operand. A 16-bit displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement

@ERn+ or @-ERn

• Register indirect with post-increment@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word

or longword access, the register value should be even.

• Register indirect with pre-decrement@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result is the address of a memory operand.

The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for

word access, or 4 for longword access. For the word or longword access, the register value

should be even.

(5) Absolute Address

@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit

absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the

entire address space.

The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the

upper 8 bits are ignored.

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