M32CSLASH8B datasheet(313/406 Pages) RENESAS

313 / 406 page

Under development

M32C/8B Group

22. Programmable I/O Ports

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 296 of 385

Table 22.1

Unassigned Pin Handling in Single-Chip Mode

NOTES:

1. P11 to P15 are provided in the 144-pin package only.

2. It is when the external clock is input to the XIN pin.

Table 22.2

Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode

NOTES:

1. P11 to P15 are provided in the 144-pin package only.

2. It is when the external clock is applied to the XIN pin.

Figure 22.17

Unassigned Pin Handling

Pin Name

Handling

P0 to P15

(excluding P8_5)(1)

Set pins to input mode and connect each pin to VSS via a resistor (pull-down),

or set pins to output mode and leave them open

XOUT(2)

Leave the pin open

NMI (P8_5)

Connect the pin to VCC1 via a resistor (pull-up)

VREF

Connect the pin to VSS

Pin Name

Handling

P1, P6 to P15

(excluding P8_5)(1)

Set pins to input mode and connect each pin to VSS via a resistor (pull-down),

or set pins to output mode and leave them open

BHE, ALE, HLDA,

XOUT(2), BCLK

Leave the pin open

HOLD, RDY

Connect the pin to VCC2 via a resistor (pull-up)

NMI(P8_5)

Connect the pin to VCC1 via a resistor (pull-up)

VREF

Connect the pin to VSS

MCU

P0 to P15(1)

(except for P8_5)

(Input mode)

(Output mode)

NMI (P8_5)

XOUT

AVCC

BYTE

AVSS

VREF

In single-chip mode

Open

VCC1

VSS

Open

(Input mode)

MCU

P1, P6 to P15(1)

(except for P8_5)

(Input mode)

(Output mode)

NMI (P8_5)

BHE

ALE

AVCC

AVSS

VREF

In memory expansion mode

and microprocessor mode

Open

VCC2

Open

(Input mode)

HLDA

XOUT

BCLK

HOLD

RDY

NOTE:

1. P11 to P15 are provided in the 144-pin package only.

VSS

VCC1

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