M32CSLASH8B datasheet(302/406 Pages) RENESAS

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b7 b6 b5 b4

Symbol

P0 to P5

P6 to P10

P11 to P15

Address

03E0h, 03E1h, 03E4h, 03E5h, 03E8h, 03E9h

03C0h, 03C1h(3), 03C4h(4), 03C5h, 03C8h

03C9h(5), 03CCh, 03CDh, 03D0h(5), 03D1h

After Reset

Undefined

Function

Bit Symbol

Bit Name

Pi_5

Pi_7

Port Pi_3 bit

Port Pi_7 bit

Pi_4

Pi_3

Port Pi_5 bit

Port Pi_6 bit

Pi_6

Port Pi Register (1, 2) (i = 0 to 15)

Port Pi_4 bit

NOTES:

1. In memory expansion mode and microprocessor mode, the Pi register corresponding to the following bus control pins cannot be

written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE, RDY.

2. Ports P11 to P15 are provided in the 144-pin package only.

3. P7_0 and P7_1 are N-channel open drain output ports. The pins are placed into high-impedance states when the corresponding bits to

P7_0 and P7_1 are set to 1.

4. The P8_5 bit is a read-only bit.

5. Nothing is implemented to bits P11_5 to P11_7 in the P11 register and the P14_7 bit in the P14 register. Write a 0. A read from these

bits returns undefined value.

Port Pi_1 bit

Pi_1

Port Pi_2 bit

Pi_2

Input mode

(The PDi_j bit (j = 0 to 7) in the PDi register = 0)

Read: Return the pin level.

Write: Write to the port latch.

Output mode

(The PDi_j bit in the PDi register = 1)

Read: Return the port latch value.

Write: Write to the port latch and the port latch

value is output from the pin.

0: "L" level

1: "H" level

Port Pi_0 bit

Pi_0

Under development

M32C/8B Group

22. Programmable I/O Ports

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 285 of 385

Figure 22.6

P0 to P15 Registers

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