M32CSLASH8B datasheet(397/406 Pages) RENESAS

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M32C/8B Group

25. Usage Notes

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 380 of 385

25.13 Programmable I/O Ports

• Pins P7_2 to P7_5, P8_0, and P8_1 have the forced cutoff function of the three-phase PWM output. When

these ports are set in output mode (port output, timer output, three-phase PWM output, serial interface output),

they are affected by the three-phase motor control timer function and the NMI pin setting. Table 25.5 shows the

INVC0 register setting, NMI pin input level, and output pin states.

Table 25.5

INVC0 Register Setting, NMI Pin Level, and Output Pin Status

−: Not affected by the bit setting nor the pin state

NOTE:

1. The INV03 bit becomes 0 after a low-level (“L”) signal is applied to the NMI pin.

• The availability of the pull-up resistors is undefined until the internal power voltage stabilizes even if the

RESET pin is held “L”.

• The input threshold level varies between the input to the port and input to the peripheral functions. If the port

function and peripheral function share the same pin, the level verified by the peripheral function and the level

obtained by reading the Port Pi register (i = 0 to 15) may vary during the process when the voltage applied to

the pin changes from “H” to “L” or from “L” to “H”.

(Technical update: TN-M16C-102-0309)

Setting Value of the INVC0 Register

NMI Pin

Input Level

Pin States of P7_2 to P7_5, P8_0, P8_1

(when set in output mode)

INV02 Bit

INV03 Bit

(three-phase motor control

timer function not used)

−−

Output functions selected using registers

PS1, PSL1, PSC, PS2, and PSL2

(three-phase motor control

timer function used)

(three-phase motor control

timer output disabled)

−

High-impedance states

(three-phase motor control

timer output enabled)(1)

Output functions selected using registers

PS1, PSL1, PSC, PS2, and PSL2

(forcibly

terminated)

High-impedance states

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