M32CSLASH8B datasheet(376/406 Pages) RENESAS

376 / 406 page

Under development

M32C/8B Group

24. Electrical Characteristics

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 359 of 385

Figure 24.10

VCC1 = VCC2 = 3.3 V Timing Diagram (4)

BCLK

CSi

ADi

BHE

ALE

td(BCLK-ALE)

18ns.max

th(BCLK-ALE)

-2ns.min

td(BCLK-CS)

18ns.max

td(AD-ALE)(1)

th(ALE-AD)(1)

tdz(RD-AD)

8ns.max

tac2(RD-DB)(1)

th(BCLK-CS)

0ns.min

th(RD-DB) 0ns.min

th(BCLK-AD)

0ns.min

td(BCLK-AD)

18ns.max

ADi /DBi

td(BCLK-RD)

18ns.max

tac2(AD-DB)(1)

th(BCLK-RD)

-3ns.min

th(RD-AD)(1)

tcyc

Address

NOTES:

1. Varies with operation frequency:

td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a

φ + bφ, n = a)

th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a

φ + bφ, n = a)

th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min

tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a

φ + bφ, m = (b x 2) - 1)

tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a

φ + bφ, p = {(a + b - 1) x 2} + 1)

NOTES:

1. Varies with operation frequency:

td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a

φ + bφ, n = a)

th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a

φ + bφ, n = a)

th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min

th(WR-DB) = (tcyc / 2 - 20) ns.min

td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a

φ + bφ, m = (b x 2) - 1)

Measurement Conditions:

- VCC1 = VCC2 = 3.0 to 3.6 V

- Input high and low voltage VIH = 1.5 V, VIL = 0.5 V

- Output high and low voltage VOH = 1.5 V, VOL = 1.5 V

Address

VCC1=VCC2=3.3V

Memory Expansion Mode and Microprocessor Mode

(when accessing an external memory space with the multiplexed bus)

Read Timing (2

φ + 2φ Bus Cycle)

tcyc=

109

f(BCLK)

BCLK

CSi

ADi

BHE

WR,WRL,WRH

Write Timing (2

φ + 2φ Bus Cycle)

td(BCLK-ALE)

18ns.max

th(BCLK-ALE)

-2ns.min

td(BCLK-CS)

18ns.max

td(AD-ALE)(2)

th(ALE-AD)(2)

td(DB-WR)(2)

th(WR-CS)(2)

td(BCLK-AD)

18ns.max

td(BCLK-WR)

18ns.max

th(BCLK-WR)

0ns.min

tcyc

Address

Data output

th(WR-DB)(2)

ADi /DBi

ALE

Address

th(BCLK-AD)

0ns.min

th(BCLK-CS)

0ns.min

th(RD-CS)(1)

Data input

tsu(DB-BCLK) 30ns.min

th(WR-AD)(2)

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