M32CSLASH8B datasheet(330/406 Pages) RENESAS

330 / 406 page

Under development

M32C/8B Group

23. Flash Memory

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 313 of 385

(5) Block Erase Command

By writing the command code xx20h in the first bus cycle and xxD0h to the highest-order even address of a

block to be erased in the second bus cycle, an erase operation (erase and verify) starts on the specified block.

The FMR00 bit in the FMR0 register can be used to determine whether an erase operation has been completed

or not. The FMR00 bit becomes 0 (busy) during the erase operation, and becomes 1 (ready) when the erase

operation is completed.

After the erase operation is completed, the FMR07 bit in the FMR0 register is used to determine whether the

erase operation is completed successfully or not. (Refer to 23.6.1.3 Error Check for details.)

Figure 23.10 shows a flow chart of block erase command.

The lock bit can protect each block from being erased inadvertently. (Refer to 23.3.1 Lock bit Protect

Function for details.)

In EW1 mode, do not execute this command to the block where the rewrite control program is stored.

In EW0 mode, the flash memory enters read status register mode when an erase operation starts.

Figure 23.10

Block Erase Command

Start

End

Error check

FMR00 = 1?

YES

Write the command code xx20h

Write xxD0h to the highest-order even address of block

Write command code and data to even address

M32C/8B bảng dữ liệu(PDF) 330 Page - Renesas Technology Corp