SH7136 datasheet(86/1160 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 10, 2008 Page 60 of 1130

REJ09B0402-0200

4.3

Clock Operating Mode

Table 4.3 shows the clock operating mode of this LSI.

Table 4.3

Clock Operating Mode

Clock I/O

Clock Operating

Mode

Source

Output

PLL Circuit

Input to Divider

EXTAL input or

crystal resonator

CK*

ON (

×8)

×8

Note:

To output the clock through the clock output (CK) pin, appropriate settings should be

made in the pin function controller (PFC). For details, refer to section 20, Pin Function

Controller (PFC).

Mode 1: The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the

PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to

generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 5

MHz to 12.5 MHz can be used, the internal clock (I

φ) frequency ranges from 10 MHz to 80 MHz.

Maximum operating frequencies:

φ = 80 MHz, Bφ = 40 MHz, Pφ = 40 MHz, MIφ = 80 MHz, and MPφ = 40 MHz

Table 4.4 shows the frequency division ratios that can be specified with FRQCR.

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