SH7136 datasheet(52/1160 Pages) RENESAS

52 / 1160 page

Section 2 CPU

Rev. 2.00 Sep. 10, 2008 Page 26 of 1130

REJ09B0402-0200

Table 2.7

Access with Displacement

Type

CPU in this LSI

Example of Other CPUs

16-bit displacement

MOV.W

@(disp,PC),R0

MOV.W

@(R0,R1),R2

........

.DATA.W H'1234

MOV.W

@(H'1234,R1),R2

Note:

Immediate data is referenced by @(disp,PC).

2.4.2

Addressing Modes

Table 2.8 lists addressing modes and effective address calculation methods.

Table 2.8

Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

direct

Effective address is register Rn.

(Operand is register Rn contents.)



indirect

@Rn

Effective address is register Rn contents.

indirect with

post-increment

@Rn+

Effective address is register Rn contents. A

constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand.

1/2/4

Rn + 1/2/4

After instruction

execution

Byte: Rn + 1

→ Rn

Word: Rn + 2

→ Rn

Longword: Rn + 4

→ Rn

indirect with

pre-decrement

@–Rn

Effective address is register Rn contents,

decremented by a constant beforehand: 1 for a

byte operand, 2 for a word operand, 4 for a

longword operand.

Rn - 1/2/4

1/2/4

Rn - 1/2/4

Byte: Rn – 1

→ Rn

Word: Rn – 2

→ Rn

Longword: Rn – 4

→ Rn

(Instruction

executed with Rn

after calculation)

SH7136 bảng dữ liệu(PDF) 52 Page - Renesas Technology Corp

SH7136 bảng dữ liệu(HTML) 52 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL