7549 datasheet(18/84 Pages) RENESAS

18 / 84 page

Rev.2.01

Oct 15, 2007

Page 18 of 81

REJ03B0202-0201

7549 Group

Fig 17. Block diagram of pins (2)

Compare output

port selection bit

Compare output

Port latch

(10) Port P13

Timer2 output

P13/T2OUT output valid bit

A/D converter

input

Key-on wakeup input selection bit

Analog input pin selection bit

Key input interrupt

(11) Port P14 - P17

(Note)

(12) Port P20, P21

Pull-up control at STP

P20/XOUT/XCOUT

Oscillation mode selection bit

(function set ROM data 1)

P21/XIN/XCIN

Note: Set to “1” the port P20 direction register.

Clock input

(13) Port P30, P31

(14) CNVss

Mode setting signal

input

QzROM programming

power supply

Reset signal input

(15) RESET

(9) Port P10, P11, P12

Data bus

Pull-up control bit

Direction

Pull-up control bit

Direction

Port latch

Data bus

Direction

Port latch

Data bus

Pull-up control bit

Direction

Port latch

Direction

Port latch

Data bus

Key-on wakeup input selection bit

Analog input pin selection bit

Key-on wakeup input selection bit

Analog input pin selection bit

A/D converter

input

Key input interrupt

A/D converter

input

Key input interrupt

Direction

Port latch

Data bus

represents a parasitic diode.

No current flow is possible. Ensure that the input voltage

to each pin does not exceed the absolute maximum rating.

Note:

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