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7547 bảng dữ liệu(PDF) 20 Page - Renesas Technology Corp |
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7547 bảng dữ liệu(HTML) 20 Page - Renesas Technology Corp |
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20 / 91 page ![]() 7547 Group Rev.1.21 Nov 15, 2006 page 20 of 89 REJ03B0156-0121 Table 8 Interrupt vector address and priority Vector addresses (Note 1) High-order Priority Low-order Interrupt request generating conditions Remarks Interrupt source FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are dis- criminated by interrupt source discrimination register. Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling, when key-on wakeup interrupt is enabled) When UART1 bus collision detection interrupt is enabled. External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Compare interrupt source is selected. When A/D conversion interrupt is enabled. STP release timer underflow (When Timer 1 interrupt is enabled) Non-maskable software interrupt At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of UART1 bus collision detection At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of Capture 0 input At detection of either rising or falling edge of Capture 1 input At compare matched At timer X underflow At timer A underflow At timer B underflow At completion of A/D conversion At timer 1 underflow At BRK instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit Serial I/O2 receive Serial I/O2 transmit INT0 INT1 Key-on wake-up/ UART1 bus collision detection (Note 3) CNTR0 Capture 0 Capture 1 Compare Timer X Timer A Timer B A/D conversion/ Timer 1 (Note 4) BRK instruction |
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