7547 datasheet(53/91 Pages) RENESAS

53 / 91 page

Rev.1.21

Nov 15, 2006

page 53 of 89

REJ03B0156-0121

7547 Group

Fig. 63 Operation waveform diagram of power-on reset circuit

Fig. 64 Operation waveform diagram of low voltage detection circuit

VCC (Note)

1 ms or les s

Power-on

Reset released

Internal reset signal

Reset

state

Note: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.

circuit output

wer-on reset

VCC

Reset voltage (Typ:1.90V)

Internal reset signal

Microcomputer starts operation

by the built-in on-chip oscillator.

Internal reset signal

SYNC

FFFC

FFFD

ADH,ADL

ADL

ADH

Address

Data

Reset address from the

vector table

On-chip oscillator

clock RING

Internal CPU clock

RESET

9 to 16 cycles of

internal CPU clock

Fig. 65 Timing diagram at reset

Power-on Reset Circuit

Reset can be automatically performed at power on (power-on re-

set) by the built-in power-on reset circuit.

In order to use the power-on reset circuit effectively, the time for

the supply voltage to rise from 0 V to 1.8 V must be set to 1 ms or

less.

____________

When the built-in power-on reset circuit is used, pull-up the RESET

pin to VCC.

Low voltage Detection Circuit

The built-in low voltage detection circuit is designed to detect a

drop in voltage and to reset the microcomputer if the power source

voltage drops below a set value (Typ.1.90 V).

The low voltage detection circuit is valid by setting “1” to bit 1 of

the function set ROM data 0.

Also, when “1” is set to bit 3 of the function set ROM data 0, the

low voltage detection circuit can be valid even in the stop mode.

The low voltage detection circuit is stopped in the stop mode by

setting “0” to this bit, so that the power dissipation is reduced.

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