 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
LFSC bảng dữ liệu(PDF) 71 Page - Lattice Semiconductor |
|
|
|||||||||||||||||||||||||||||
LFSC bảng dữ liệu(HTML) 71 Page - Lattice Semiconductor |
|
|
71 / 237 page  3-27 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet LatticeSC/M sysCONFIG Port Timing Over Recommended Operating Conditions Parameter Description Min. Max. Units General Configuration Timing tSMODE M[3:0] Setup Time to INITN High 0 — ns tHMODE M[3:0] Hold Time from INITN High 600 — ns tRW RESETN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at 0.95V) —ns tPGW PROGRAMN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at 0.95V) —ns fESB_CLK_FRQ System Bus ESB_CLK Frequency (No Wait States) — 133 MHz sysCONFIG Master Parallel Configuration Mode tSMB D[7:0] Setup Time to RCLK High 6 — ns tHMB D[7:0] Hold Time to RCLK High 0 — ns tCLMB RCLK Low Time (Non-compressed Bitstreams) 0.5 0.5 CCLK periods RCLK Low Time (Compressed Bitstreams) 0.5 7.5 CCLK periods tCHMB RCLK High Time 0.5 0.5 CCLK periods sysCONFIG SPI Port tCFGX INITN High to CSCK Low — 80 ns tCSSPI INITN High to CSSPIN Low 0 2 µs tSCK CSCK Low before CSSPIN Low 0 — ns tSOCDO CSCK Low to Output Valid — 15 ns tCSPID CSSPIN Low to CSCK high Setup Time — 15 ns fMAXSPI Max CCLK Frequency - SPI Flash Fast Read Opcode (0x0B) (SPIFASTN=0) — 50 MHz tSUSPI SOSPI/D0 Data Setup Time Before CSCK 7 — ns tHSPI SOSPI/D0 Data Hold Time After CSCK 2 — ns Master Clock Frequency Selected value - 30% Selected value + 30% MHz Duty Cycle 40 60 % sysCONFIG Master Serial Configuration Mode tSMS DIN Setup Time 4.4 — ns tHMS DIN Hold Time 0 — ns fCMS CCLK Frequency (No Divider) 90 190 MHz fC_DIV CCLK Frequency (Div 128) 0.70 1.48 MHz tD CCLK to DOUT Delay — 7.5 ns sysCONFIG Master Parallel Configuration Mode tAVMP RCLK to Address Valid — 10 ns tSMP D[7:0] Setup Time to RCLK High 6 — ns tHMP D[7:0] Hold Time to RCLK High 0 — ns tCLMP RCLK Low Time (Non-compressed Bitstream) 7.5 7.5 CCLK periods RCLK Low Time (Compressed Bitstream) 0.5 63.5 tCHMP RCLK High Time 0.5 0.5 CCLK periods tDMP CCLK to DOUT — 7.5 ns |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
