STM8AF51XX datasheet(79/100 Pages) STMICROELECTRONICS

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STM8AF61xx, STM8AF51xx

Electrical characteristics

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11.3.8

SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage

conditions. tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 33.

SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

tsu(NSS)

(1)

NSS setup time

Slave mode

4*TMASTER

th(NSS)

(1)

NSS hold time

Slave mode

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master mode,

fMASTER = 16 MHz, fSCK= 8 MHz

110

140

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master mode

Slave mode

th(MI)

(1)

th(SI)

(1)

Data input hold time

Master mode,

fMASTER = 16 MHz, fSCK = 8 MHz

Slave mode,

fMASTER = 16 MHz, fSCK = 8 MHz

ta(SO)

(1)(2)

Data output access time

Slave mode,

fMASTER = 16 MHz, fSCK = 8 MHz

400

Slave mode

4*tMASTER

tdis(SO)

(1)(3)

Data output disable time

Slave mode

tv(SO)

(1)

Data output valid time

Slave mode (after enable edge),

fMASTER = 16 MHz, fSCK = 8 MHz

100

tv(MO)

(1)

Data output valid time

Master mode (after enable edge),

fMASTER = 16 MHz, fSCK = 8 MHz

th(SO)

(1)

Data output hold time

Slave mode (after enable edge)

100

th(MO)

(1)

Master mode (after enable edge)

Values based on design simulation and/or characterization results, and not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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