C167CS-4RM datasheet(66/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-16

V2.0, 2000-07

The Processor Status Word PSW

This bit-addressable register reflects the current state of the microcontroller. Two groups

of bits represent the current ALU status, and the current CPU interrupt status. A separate

bit (USR0) within register PSW is provided as a general purpose user flag.

ALU Status (N, C, V, Z, E, MULIP)

The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status due to the last

recently performed ALU operation. They are set by most of the instructions due to

specific rules, which depend on the ALU or data movement operation performed by an

instruction.

PSW

Program Status Word

SFR (FF10H/88H)

Reset Value: 0000H

9876

543210

ILVL

IEN HLD

USR0 MUL

rwh

Bit

Function

Negative Result

Set, when the result of an ALU operation is negative.

Carry Flag

Set, when the result of an ALU operation produces a carry bit.

Overflow Result

Set, when the result of an ALU operation produces an overflow.

ZZero Flag

Set, when the result of an ALU operation is zero.

End of Table Flag

Set, when the source operand of an instruction is 8000H or 80H.

MULIP

Multiplication/Division In Progress

There is no multiplication/division in progress.

A multiplication/division has been interrupted.

USR0

User General Purpose Flag

May be used by the application software.

HLDEN, ILVL,

IEN

Interrupt and EBC Control Fields

Define the response to interrupt requests and enable external bus

arbitration. (Described in Chapter 5)

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