C167CS-4RM datasheet(28/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-11

V2.0, 2000-07

2.3

The On-Chip Peripheral Blocks

The C166 Family clearly separates peripherals from the core. This structure permits the

maximum number of operations to be performed in parallel and allows peripherals to be

added or deleted from family members without modifications to the core. Each functional

block processes data independently and communicates information over common

buses. Peripherals are controlled by data written to the respective Special Function

Registers (SFRs). These SFRs are located either within the standard SFR area

(00’FE00H … 00’FFFFH) or within the extended ESFR area (00’F000H … 00’F1FFH).

These built in peripherals either allow the CPU to interface with the external world, or

provide functions on-chip that otherwise were to be added externally in the respective

system.

The C167CS generic peripherals are:

• Two General Purpose Timer Blocks (GPT1 and GPT2)

• Two Serial Interfaces (ASC0 and SSC)

• A Watchdog Timer

• Two 16-channel Capture/Compare units (CAPCOM1 and CAPCOM2)

• A 4-channel Pulse Width Modulation unit

• A 10-bit Analog/Digital Converter

• A Real Time Clock

• Nine IO ports with a total of 111 IO lines

Each peripheral also contains a set of Special Function Registers (SFRs), which control

the functionality of the peripheral and temporarily store intermediate data results. Each

peripheral has an associated set of status flags. Individually selected clock signals are

generated for each peripheral from binary multiples of the CPU clock.

Peripheral Interfaces

The on-chip peripherals generally have two different types of interfaces, an interface to

the CPU and an interface to external hardware. Communication between CPU and

peripherals is performed through Special Function Registers (SFRs) and interrupts. The

SFRs serve as control/status and data registers for the peripherals. Interrupt requests

are generated by the peripherals based on specific events which occur during their

operation (e.g. operation complete, error, etc.).

For interfacing with external hardware, specific pins of the parallel ports are used, when

an input or output function has been selected for a peripheral. During this time, the port

pins are controlled by the peripheral (when used as outputs) or by the external hardware

which controls the peripheral (when used as inputs). This is called the ‘alternate (input

or output) function’ of a port pin, in contrast to its function as a general purpose IO pin.

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