C167CS-4RM datasheet(51/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-1

V2.0, 2000-07

The Central Processing Unit (CPU)

Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the

arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and

to store the previously calculated results. As the CPU is the main engine of the C167CS

controller, it is also affected by certain actions of the peripheral subsystem.

Since a four stage pipeline is implemented in the C167CS, up to four instructions can be

processed in parallel. Most instructions of the C167CS are executed in one machine

cycle (2 CPU clock periods) due to this parallelism.

This chapter describes how the pipeline works for sequential and branch instructions in

general, and which hardware provisions have been made to speed the execution of jump

instructions in particular. The general instruction timing is described including standard

and exceptional timing.

While internal memory accesses are normally performed by the CPU itself, external

peripheral or memory accesses are performed by a particular on-chip External Bus

Controller (EBC), which is automatically invoked by the CPU whenever a code or data

address refers to the external address space.

Figure 4-1

CPU Block Diagram

MCB02147

CPU

STKOV

STKUN

Instr. Reg.

Instr. Ptr.

Exec. Unit

4-Stage

Pipeline

MDH

MDL

PSW

SYSCON

Context Ptr.

Mul/Div-HW

R15

General

Purpose

Registers

Bit-Mask Gen

Barrel - Shifter

ALU

(16-bit)

Data Page Ptr.

Code Seg. Ptr.

Internal

RAM

R15

ROM

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSEL 4

ADDRSEL 3

ADDRSEL 2

ADDRSEL 1

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