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ST72E121 bảng dữ liệu(PDF) 57 Page - STMicroelectronics

tên linh kiện ST72E121
Giải thích chi tiết về linh kiện  8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
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ST72E121 bảng dữ liệu(HTML) 57 Page - STMicroelectronics

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ST72E121 ST72T121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.5 Low Power Modes
4.4.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the I-bit in
the CC register is reset (RIM instruction).
Mode
Description
WAIT
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
HALT
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Transmit Data Register Empty
TDRE
TIE
Yes
No
Transmission Complete
TC
TCIE
Yes
No
Received Data Ready to be Read
RDRF
RIE
Yes
No
Overrrun Error Detected
OR
Yes
No
Idle Line Detected
IDLE
ILIE
Yes
No
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