ST72E121 datasheet(73/92 Pages) STMICROELECTRONICS

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ST72E121 ST72T121

SERIAL PERIPHERAL INTERFACE (Cont’d)

STATUS REGISTER (SR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the CR register. It is cleared by a soft-

ware sequence (an access to the SR register fol-

lowed by a read or write to the DR register).

0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the DR

Bit 6 = WCOL

Write Collision status.

This bit is set by hardware when a write to the DR

cleared by a software sequence (see Figure 39).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF

Mode Fault flag.

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 4.5.4.5

Master Mode Fault). An SPI interrupt can be gen-

erated if SPIE=1 in the CR register. This bit is

cleared by a software sequence (An access to the

SR register while MODF=1 followed by a write to

the CR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bits 3-0 = Unused.

DATA I/O REGISTER (DR)

Read/Write

Reset Value: Undefined

The DR register is used to transmit and receive

data on the serial bus. In the master device only a

write to this register will initiate transmission/re-

ception of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

the serial peripheral data I/O register, the buffer is

actually being read.

Warning:

A write to the DR register places data directly into

the shift register for transmission.

A write to the the DR register returns the value lo-

cated in the buffer and not the contents of the shift

SPIF

WCOL

MODF

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