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ST72E121 bảng dữ liệu(PDF) 71 Page - STMicroelectronics

tên linh kiện ST72E121
Giải thích chi tiết về linh kiện  8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
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ST72E121 bảng dữ liệu(HTML) 71 Page - STMicroelectronics

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ST72E121 ST72T121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.5 Low Power Modes
4.5.6 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
Mode
Description
WAIT
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
HALT
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
SPI End of Transfer Event
SPIF
SPIE
Yes
No
Master Mode Fault Event
MODF
Yes
No
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