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HB2000ES bảng dữ liệu(PDF) 11 Page - NXP Semiconductors |
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HB2000ES bảng dữ liệu(HTML) 11 Page - NXP Semiconductors |
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11 / 34 page ![]() NXP Semiconductors KTFRDMHB2000ESEVMUG FRDM-HB2000ESEVM evaluation board KTFRDMHB2000ESEVMUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. User guide Rev. 2 — 11 June 2018 11 / 34 4.6 Jumper definitions Figure 7 illustrates the evaluation board jumper locations. Table 4 explains the function of each position. Bold fonts in the jumper position column indicate the default settings for use with the FRDM-KL25Z. DIS VDD CFB ENBL IN2 IN1 EX_IN CFB_R VDD_REG MOSI SCLK MISO CS_B VDDQ FS_B Figure 7. Jumper definitions Table 4. Jumper locations Name Signal Jumper position Connection 1−2 IN1 control through MCU parallel output on J10 pin 1 (DATA0) J1 IN1 2−3 IN1 control through external input on J15 pin 1 1−2 DIS control through MCU parallel output on J10 pin 13 (CTRL1) J2 DIS 2−3 DIS connected to GND to keep the outputs enabled 1−2 IN2 control through MCU parallel output on J10 pin 3 (DATA1) J3 IN2 2−3 IN2 control through external input on J15 pin 2 1−2 CS_B control through MCU SPI output J10 pin 6 (SPI_CS_B) J4 CS_B 2−3 CS_B pulled up to VDD for operation without SPI 1−2 ENBL control through MCU parallel output J10 pin 11 (CTRL0) J5 ENBL 2−3 ENBL pulled up to VDD to keep the outputs enabled 1−2 SPI clock SCLK from MCU J10 pin 12 (SPI_SCLK) J6 SCLK 2−3 SCLK connected to GND for operation without SPI 1−2 MOSI control through MCU SPI output J10 pin 8 (SPI_MOSI) J7 MOSI 2−3 MOSI connected to GND for operation without SPI |
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